In modern logic circuits it is often necessary to apply signals of a relatively low voltage level to energize and operate one type of electrical component, for example digital logic components, and signals of a relatively higher voltage level to operate and energize other types of related components, for example capacitors. In practice, it is therefore often necessary to apply a signal which has different voltage levels at different portions of a circuit.
Modern implantable heart pacemakers provide one example of relatively sophisticated electronic devices which require operational signals at different voltage levels. In such a device, it is not unusual to require a low voltage level of for example 2 volts to energize certain portions of a complex logic circuit and a greater voltage of for example 8 volts to activate other portions of the circuit. Thus, relatively low level voltage signals are applied to energize and operate TTL logic circuits which control the pacemaker, while more powerful signals are required to energize capacitors which stimulate the heart.
Implanted heart pacemakers must operate over a period of years on power supplied by relatively small batteries disposed within the housing of the pacemaker. It is therefore necessary to provide a pacemaker which is reliable, stable and which also consumes a relatively low dynamic current in order to reduce the drain on the batteries. As a practical matter, the pacemaker should also have a relatively low static current consumption so that the drain on the batteries is minimized when the pacemaker is in a quiescent or rest state.
Pacemakers and like devices have employed CMOS level shifting circuits to provide the bilevel voltages required in operation. Such circuits have typically required relatively large and powerful P-channel transistor switching devices to operate with lower power P-channel and N-channel digital logic devices. The use of the relatively large and powerful P-channel devices results in a relatively large current drain when the level shifter circuit changes state. The relatively high capacitance of the large P-channel devices also tends to reduce the speed of operation of the level shifting circuit. Moreover, the relatively large physical size of the devices is a disadvantage in apparatus, for example heart pacemakers, which must be made as small as possible.
Finally, in existing level shifting circuits, the quiescent or rest state of the circuit is characterized by a perceptible leakage current which provides a constant drain on the power supply of the circuit. This is a serious disadvantage for self-contained powered apparatus such as heart pacemakers.
Accordingly, it is an object of the invention to provide a level shifting logic circuit which operates without requiring the use of relatively large P-channel devices.
A further object of the invention is to provide such a circuit which operates with relatively small P-channel and N-channel transistor devices to minimize the size and power consumption of the circuit.
A further object of the invention is to provide a level shifting circuit which minimizes the capacitance of operational components of the circuit and which therefore increases the speed of operation of the circuit.
Another object of the invention is to provide such a level shifting circuit which minimizes leakage current in the quiescent or rest state and which therefore reduces the power consumption of the circuit and promotes a longer life for any self-contained power supply for the circuit.
A further object of the invention is to provide a relatively low power and relatively fast level shifting circuit which is well-suited for shifting the voltage level of operational signals in an implanted heart pacemaker.
These and other objects of the invention will become apparent from a review of the specification which follows and of the drawings which are described hereafter.